1. Field of the Invention
Example embodiments of the present invention relates to a method of forming a silicon-rich nanocrystalline structure and a method of manufacturing a non-volatile semiconductor device using the same. More particularly, example embodiments the present invention relates to a method of forming a silicon-rich nanocrystalline structure by an atomic layer deposition (ALD) process, and a method of manufacturing a non-volatile semiconductor device using the same.
2. Description of the Related Art
Generally, semiconductor memory devices are classified into volatile semiconductor memory devices such as dynamic random access memory (DRAM) devices and static random access memory (SRAM) devices that lose data stored therein as time elapses, and non-volatile semiconductor memory devices such as read only memory (ROM) devices that continuously possess data stored therein regardless of time. Further, the data may be relatively rapidly inputted/outputted into/from the volatile semiconductor memory devices. On the contrary, the data may be relatively slowly inputted/outputted into/from the non-volatile semiconductor memory devices. An electrically erasable and programmable read only memory (EEPROM) device and a flash memory device among the non-volatile semiconductor memory devices into which the data may be electrically inputted and from which the data may be electrically outputted have been widely used in current semiconductor memory devices.
The flash memory device usually includes a memory cell that has a vertically stacked gate structure. The vertically stacked gate structure includes a floating gate formed on a semiconductor substrate. The vertically stacked gate structure further includes at least one tunnel dielectric layer or dielectric interlayer, and a control gate formed over the floating gate or at a peripheral of the floating gate.
In the non-volatile semiconductor device including a memory cell that has the vertically stacked gate structure, hot electrons generated in a channel region may overcome an energy barrier of the tunnel dielectric layer, and then may be injected into the floating gate so that the memory cell may be programmed. When the hot electrons in the floating gate are removed by Fowler-Nordheim (FN) tunneling mechanism, the data programmed in the memory cell may be erased.
When a high voltage is applied to the control gate to cause a potential difference between a source region and a drain region, the hot electrons generated in the channel region adjacent to the drain region may overcome the energy barrier, and then may be injected into the floating gate. Further, when a high voltage is applied to the source region and a voltage of about 0V is simultaneously applied to the control gate and the semiconductor substrate, the hot electrons in the floating gate may be removed by the F-N tunneling mechanism between the source region and the floating gate.
However, there are problems in relation to the electron retention in the non-volatile semiconductor memory device having the vertically stacked gate structure. To maintain the data stored in the memory cell, the hot electrons in the floating gate are maintained. When defects such as pinholes exist in the tunnel dielectric layer, the hot electrons in the floating gate may come out through the defects.
Further, in the vertically stacked memory cell, a tunnel junction through which the hot electrons pass is formed by means of an insulation layer such as an oxide layer having a high energy barrier in a band diagram. Since the energy barrier with respect to the hot electrons is very high, it is required to reduce a thickness of the energy barrier for improving an electron-tunneling rate through the tunnel junction. Thus, the tunnel dielectric layer may have a precisely thin thickness. However, the formation of the tunnel dielectric layer having the thin thickness causes difficulty in manufacturing uniform semiconductor devices and causes inferior reliability of the tunnel dielectric layer.
Recently, to solve the above-mentioned problems regarding the vertically stacked gate structure, a non-volatile semiconductor memory device including a silicon-rich oxide layer as a charge trapping layer has been developed.
The silicon-rich oxide layer generally includes an oxide layer having numerous silicon nanocrystals therein. The silicon nanocrystals in the silicon-rich oxide layer serve as a floating gate of the non-volatile semiconductor device.
The silicon nanocrystals trap or detrap hot electrons by tunneling mechanism. Additionally, the silicon nanocrystals are electrically separated from one another. While the non-volatile semiconductor memory cell is programmed, the electrons are injected into the silicon nanocrystals of the silicon-rich oxide layer. Since the silicon nanocrystals are electrically separated, electro-migration between the silicon nanocrystals may be restricted. Thus, although defects are partially generated in silicon-rich oxide layer, a leakage current caused by the defects may not affect on the electrons trapped in the silicon nanocrystals in the silicon-rich oxide layer.
In the non-volatile semiconductor memory device :including the silicon-rich oxide layer having the silicon nanocrystals, a multi-state memory cell for storing at least one data bit therein may be embodied using a variation of a threshold voltage accompanied with one electron stored in one silicon nanocrystal.
The silicon-rich oxide layer may be formed using a silane (SiH4) gas and a nitrous oxide (N2O) gas through a low pressure chemical vapor deposition (LPCVD) process, a plasma enhanced chemical vapor deposition (PECVD) process or a silicon implantation process. For example, a method of forming the silicon-rich oxide layer is disclosed in U.S. Pat. No. 6,274,429 (issued to Sudhanshu), U.S. Pat. No. 5,726,070 (issued to Hong), U.S. Pat. No. 5,763,937 (issued to Vivek), U.S. Pat. No. 6,774,061 (issued to Patti) and U.S. Pat. No. 6,458,722 (issued to Kapoor).
However, in the formation of the silicon-rich oxide layer using the LPCVD process, bonds of silicon-oxygen (Si—O) may be generated more than bonds of silicon-silicon (Si—Si) in numbers after the silane (SiH4) gas and the nitrous oxide (N2O) gas are chemically reacted with each other. Thus, there is a limit to increase a silicon content of the silicon-rich oxide layer.
Meanwhile, in the formation of the silicon-rich oxide layer on a semiconductor substrate having a pattern thereon through the PECVD process, the silicon-rich oxide layer may have a poor step coverage due to a plasma employed in the PECVD process. Further, portions of the silicon-rich oxide layer on a sidewall of the pattern and a bottom of the pattern may have silicon contents different from those of other portions of the silicon-rich oxide layer.
In the formation of the silicon-rich oxide layer by the silicon implantation process in which silicon atoms are injected into an oxide layer, a leakage current may be generated because of damages to the silicon-rich oxide layer caused by the injection of the silicon atoms. Further, it is very difficult to control densities and sizes of the silicon nanocrystals in the silicon-rich oxide layer.